1. Field of the Invention
The present invention relates to a halftone mask, and more particularly to a halftone mask that is adaptive for preventing a residual photo-resist pattern, and a fabricating method thereof.
Further, the present invention relates to a fabricating method of a display device that is adaptive for improving uniformity and precision of signal and electrode pattern of the display device by using the halftone mask.
2. Description of the Related Art
A liquid crystal display device controls a light transmittance of a liquid crystal by controlling an electric field, thereby displaying a picture. The liquid crystal display device includes a liquid crystal display panel where liquid crystal cells are arranged in a matrix shape, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel includes a thin film transistor substrate, a color filter substrate, and a liquid crystal layer injected between the substrates.
The color filter substrate realizes the color of the liquid crystal cells, and includes a black matrix formed in a border part between color filters and liquid crystal cells, a common electrode for commonly supplying a reference voltage to the liquid crystal cells, and an alignment film spread thereover.
The thin film transistor substrate and the color filter substrate are bonded together after being made separately. A liquid crystal is injected and the bonded substrates are sealed.
In such a liquid crystal display panel, the fabricating process of the thin film transistor is complicated and is an important factor of the high manufacturing cost of the liquid crystal display panel because the thin film transistor substrate includes a semiconductor process and requires a plurality of mask processes. To solve this problem, the thin film transistor substrate has been developed in a direction to reduce the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photo-resist stripping process, an inspection process, etc. Accordingly, a four-mask process has recently been on the rise, wherein the four-mask process is reduced by one mask process from the five-mask process which is a standard mask process of the thin film transistor substrate.
FIG. 1A is a cross-sectional view of a thin film transistor substrate which is made by adopting a four-mask process. Referring to FIG. 1A, the thin film transistor substrate includes a gate line 2 and a data line 4 which are formed on a lower substrate to cross each other with a gate insulating film 44 therebetween; a thin film transistor 6 formed at each crossing part thereof; and a pixel electrode 18 formed in a cell area which is provided by the crossing structure. In addition, the thin film transistor substrate includes a storage capacitor 20 formed in an overlapping part of the pixel electrode 18 and the pre-stage gate line 2; a gate pad connected to the gate line 2; and a data pad connected to the data line 4.
The thin film transistor 6 receives a pixel signal supplied to the data line 4 to be applied to the pixel electrode 18 in response to a scan signal supplied to the gate line 2. The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2; a source electrode 10 connected to the data line 4; a drain electrode 12 connected to the pixel electrode 16; and an active layer which overlaps with the gate electrode 8 and forms a channel between the source electrode 10 and the drain electrode 12.
The active layer 14, which overlaps with the source electrode 10 and the drain electrode 12 and includes a channel part between the source electrode 10 and the drain electrode 12, is also formed to overlap with the data line 4, a data pad lower electrode 36 and a storage electrode 22. An ohmic contact layer 48 is further formed on the active layer 14 to be in ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, the data pad lower electrode 36 and the storage electrode 22.
The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 through a first contact hole 16 which penetrates a passivation film 50. The pixel electrode 18 generates a potential difference with a common electrode which is formed on an upper substrate (not shown), by applying the pixel signal on the pixel electrode 18. The potential difference causes a liquid crystal located between the thin film transistor substrate and the upper substrate to rotate by dielectric anisotropy so as to transmit the light, which is incident through the pixel electrode 18 from a light source (not shown), to the upper substrate.
The storage capacitor 20 includes a pre-stage gate line 2; a storage upper electrode 22 which overlaps with the gate line 2 with the gate insulating film 44, the active layer 14 and the ohmic contact layer 48 therebetween; and the pixel electrode 18 which overlaps with the storage upper electrode 22 with the passivation film 50 therebetween and is connected thereto through a second contact hole 24 which penetrates the passivation film 50. The storage capacitor 20 keeps the pixel signal applied on the pixel electrode 18 to be stable until the next pixel signal is charged.
The gate line 2 is connected to a gate driver (not shown) through a gate pad 26. The gate pad 26 includes a gate pad lower electrode 28 extending from the gate line 2, and a gate pad upper electrode 32 connected to the gate pad lower electrode 28 through a third contact hole 30 which penetrates the gate insulating film 44 and the passivation film 50.
The data line 4 is connected to a data driver (not shown) through a data pad 34. The data pad 34 includes a data pad lower electrode 36 extending from the data line 4; and a data pad upper electrode 40 connected to the data pad lower electrode 36 through a fourth contact hole 38 which penetrates the passivation film 50.
The thin film transistor which has such a configuration and is formed by the four-mask process simplifies the fabricating process by using a halftone mask. If the halftone mask is used, the data line 4, the source electrode 10, the drain electrode 12, the storage electrode 22, the data pad lower electrode 36, and a semiconductor pattern including the ohmic contact layer 48 and the active layer 14 can be formed by one mask process.
FIG. 1B is a cross-sectional view of a part of the thin film transistor substrate to illustrate the step of forming a photo-resist pattern by using a halftone mask in the fabricating process of the thin film transistor substrate shown in FIG. 1A.
A halftone mask 160 used herein includes a transparent quartz SiO2 substrate 166; and a shielding layer 162 and a partial transmission layer 164 which are formed thereon. Herein, the shielding layer 162 is located in an area where the gate pattern is to be formed, to intercept ultraviolet ray UV, thereby leaving a first photo-resist pattern 168a after development. The partial transmission layer 164 is located in an area where the storage lower electrode is to be formed, to partially transmit the ultraviolet ray UV, thereby leaving a second photo-resist pattern 168b which is lower than the first photo-resist pattern 168a, after development. The shielding layer 162 is formed of a metal such as chrome Cr, chrome oxide CrOx, etc, and the partial transmission layer 164 is formed of molybdenum silicide MoSix, etc. When forming the first and second photo-resist patterns 168a, 168b, a stepped part of a border part of the first and second photo-resist patterns 168a, 168b is formed to have a gradient. Thus, a residual photo-resist material 169 is left even after going through an ashing process and an etching process. The photo-resist material 169 left in this way causes a pattern, which is to be formed later, to be formed non-uniformly. Therefore, the non-uniform pattern deteriorates the precision of the fabricating process of the display device.
Such a problem may also happen to another case of forming the photo-resist pattern PR by using the existing halftone mask 260 as shown in FIG. 2 as well as to the case of forming the thin film transistor substrate as described above.
FIG. 2 is a diagram showing a problem in more detail when the photo-resist pattern is formed by using the existing halftone mask.
Referring to FIG. 2, a part where a stepped difference of the photo-resist pattern is to be formed is a border part of a W1 area and a W2 area which corresponds to a border part of a shielding pattern part 262 and a halftone pattern part 264. However, if the photo-resist pattern PR is formed by using the existing halftone mask having the halftone pattern part 264 of single layer structure, the stepped difference part of the photo-resist pattern PR will have a gradient, thereby forming the W2 area where the stepped difference width is broadened. The stepped difference width W2 part of the photo-resist pattern broadly formed in this way will not be removed after the ashing process, thereby decreasing the uniformity and precision of the signal and electrode pattern to be formed.